Abstract
Objectives
This paper presents a novel array-chip technology used to monitor the physical properties of dental composites in situ . The DECAY chip ( D egradation via E lectro c hemical A rra y ) leverages microfabrication techniques to construct a uniform array of recessed wells that may be filled with dental restorative materials (e.g. composite or amalgam) and analyzed electrochemically in solution.
Methods
The array enables the uniform preparation of multiple specimens and reference controls on a common substrate, all of which may be simultaneously evaluated. The DECAY-chip presented here consists of a 3 × 3 array of 100 μm deep wells, and is used to monitor the degradation of a common dental composite as a function of time.
Results
The data correlate changes in the measured dielectric properties to surface and bulk changes as the composite is exposed to an ethanol:DI mixture (75% ethanol). A model for the system is presented, as are future plans to simplify the methodology for rapid materials screening and in vitro analyses.
Significance
This in situ diagnostic chip will enable evaluation of composite specimens, tested under a wide range of simulated oral environments. It may also serve as a screening platform for new composite formulations and aid in the study of materials degradation and failure mechanisms.
1
Introduction
Over the past decade, the clinical placement of dental composites for posterior restorations has dramatically increased as amalgam use has declined. Several factors are responsible for this: (1) esthetics, (2) improved materials and bonding systems, and (3) improved methods of composite placement, ultimately improving contour and proximal contacts . Resin composites comprise a blend of hard inorganic particles bound together by a relatively soft resin matrix. The three main components are: (1) resin matrix (consisting of monomer system, initiator system for free radical polymerization, and stabilizers from maximizing storage stability of the uncured resin and chemical stability of the cured resin; (2) inorganic filler consisting of particles (glass, quartz, fumed silica, and/or metal-oxides); and (3) coupling agent (organosilane chemically bonding particle with matrix) . As noted in comprehensive review articles including but not limited to , dental composites have evolved significantly both chemically and physically. However, there are still drawbacks, including polymerization shrinkage, potential failure at resin–dentin interface leading to secondary caries, and relatively high coefficient of thermal expansion when compared to metal-based restorations. Because of this, there is growing interest in developing standard characterization techniques for testing composite degradation in situ for purposes of both materials development and evaluation.
Dental composites and other restorative materials are designed to resist degradation, however most non-destructive analytical techniques, such as gravimetric or optical, are not sensitive enough to detect and monitor degradation, even for in vitro models. Electrochemical impedance spectroscopy (EIS) has been shown to be a highly sensitive analytical technique when evaluating degradation of polymers and/or composite materials . The technique is especially sensitive to the following two common modes of materials degradation: an initial decline in the polymer-matrix resistance due to partial ingress of the electrolyte; and further bulk deterioration due to microorganism (biofilm) activity . Both degradation modes may be detected and monitored independently. EIS is also sensitive to surface reactions and may be used to detect and independently monitor biofilm activity , however those studies are outside the scope of this report and the subject of future research using this array-chip technology.
This paper presents the use of a microfabricated chip with multiple, uniformly etched recesses, enabling AC impedance to be measured on multiple dental composite specimens and control constructs independently and simultaneously. The study uses EIS to measure and subsequently model the impedance elements (resistive and capacitive) of the composite-filled chip in solution. The research team used conventional microfabrication and thin-film processing techniques to construct the array of independently addressable, etched recesses (wells), into which composite, or some other material may be placed. This DECAY chip ( D egradation via E lectro c hemical A nal y sis) enables EIS and other electronic analyses to be performed on up to nine different specimens in a parallel or serial manner. The chip standardizes both specimen size (100 μm deep, 3 mm × 3 mm wells in the chip tested here) and reference materials used in the analysis.
The DECAY chips, shown in Fig. 1 , were designed such that when filled with common dental composite (e.g. Aelite All-Purpose used here) the capacitance of the system will be dominated by the properties of the composite, relative to the reference (Parylene C—used here). Therefore, small changes in dielectric properties of the composite may be interpreted via EIS analysis. The system may be modeled using the simple circuit diagram shown in Fig. 2 . The composite can be modeled as a parallel combination of capacitance and resistance, as can the solution boundary layer or biofilm . By comparing the EIS data to this model it is possible to detect, independently changes in both the surface layer (i.e. changes in double-layer) as well as in the composite itself. The 3 × 3 array also allows for a standard reference material (e.g. Parylene C) to be used in order to further differentiate between any surface layer changes (e.g. biofilm formation) on a non-reactive surface and composite material degradation. Furthermore, the chip may be used to screen multiple composite specimens or compositions simultaneously.
2
Materials and methods
The DECAY chips shown in Fig. 1 were fabricated on 4″ diameter Si wafers. Fig. 3 , is a schematic representation of the process flow. The recessed wells were formed by first masking the silicon with 200 nm thick silicon nitride (Si x N y deposited by plasma enhanced chemical vapor deposition). In this case, the chips were patterned with 3 mm × 3 mm openings, however well dimension is easily varied, chip-to-chip or across the chip. The Si wafer is then exposed to a KOH anisotropic etch, resulting in uniformly square etched wells with 54° sidewalls when using Si(1 0 0) substrates. The wells were etched to a depth of 100 μm and then rinsed in DI water. The wafers were then coated with a thin (500 nm) silicon oxide (Si x O y ) in order to electrically isolate the subsequent metal layers from the silicon and each other. After that, gold (Au) was deposited (electron-beam deposition) and patterned so that it was in the bottom and sides of the etched wells, and was routed back to the edge connector tabs at one end of the chip (black arrow shown in Fig. 1 ). The edge connectors enabled independent contact to each of the 9 wells via gold traces routed through the chip, as shown in Fig. 1 . Lastly, a thin layer of Parylene C (a stable, reference dielectric material) was deposited (chemical vapor deposition) over the entire wafer, exposing only the connector tabs at the edge of the chips. Following fabrication, the individual chips may be diced from the wafers and stored for future testing. In this preliminary evaluation, Aelite All-Purpose dental composite (Bisco, Inc., Schaumburg, IL) was packed into 5 of the 9 test-wells (red arrow in Fig. 1 ) and light-cured for 40 s at 500 mW/cm 2 (per manufacturer’s instructions) (For interpretation of the references to color in this figure, the reader is referred to the web version of the article.).
Electrochemical measurements were made in a compact, multi-port cell in the 3-wire configuration, shown schematically in Fig. 4 . Teflon end caps are designed to interface the DECAY chip with the solution environment on one end of the cell, and ports on the opposing end for affixing a high surface area Pt counter electrode and positioning a Ag/AgCl (in saturated KCl) reference electrode directly in front of the chip. The end caps are coupled to a 25 mm DIA quartz tube with additional ports for managing the test solution. An optical micrograph of the mounted chip is shown in Fig. 5 .
Cyclic-voltammetry (CV) measurements were made using a Solartron Analytical SI 1287 Electrochemical Interface and CorrWare ® software was used to control the system (Scribner Associates, Inc., Southern Pines, NC). CorrView software was used for analyzing the data (Scribner Associates, Inc.). CV cycles were carried out from −0.1 to 1.0 V at a scan rate of 25 mV/s and initiated at the open circuit potential (OCP). Three cycles were obtained to establish the general characteristics of the CV trace. Electrochemical impedance spectroscopy (EIS) was performed using a Solartron Analytical 1252A Frequency Response Analyzer and ZPlot ® software used to control the system (Scribner Associates, Inc.). The measurements were performed at 0.5 V based on observation of reproducible CV data and a sinusoidal voltage of 10 mV was applied. ZView2 software (Scribner Associates, Inc.) automatically generated bode plots, consisting of impedance magnitude and phase angle, and plotted as a function of frequency from 1 Hz to 100 kHz. Nyquist plots showing the imaginary and real components of impedance over the same frequency range were also derived. An equivalent circuit model was then proposed (representing the electrical components of the DECAY chip, composite filler, and solution properties), and ZView2 allowed for the fitting of the EIS data to the model for subsequent analysis. Following both CV and impedance measurements, the ports were sealed and the specimens remained in solution until the next series of measurements.
2
Materials and methods
The DECAY chips shown in Fig. 1 were fabricated on 4″ diameter Si wafers. Fig. 3 , is a schematic representation of the process flow. The recessed wells were formed by first masking the silicon with 200 nm thick silicon nitride (Si x N y deposited by plasma enhanced chemical vapor deposition). In this case, the chips were patterned with 3 mm × 3 mm openings, however well dimension is easily varied, chip-to-chip or across the chip. The Si wafer is then exposed to a KOH anisotropic etch, resulting in uniformly square etched wells with 54° sidewalls when using Si(1 0 0) substrates. The wells were etched to a depth of 100 μm and then rinsed in DI water. The wafers were then coated with a thin (500 nm) silicon oxide (Si x O y ) in order to electrically isolate the subsequent metal layers from the silicon and each other. After that, gold (Au) was deposited (electron-beam deposition) and patterned so that it was in the bottom and sides of the etched wells, and was routed back to the edge connector tabs at one end of the chip (black arrow shown in Fig. 1 ). The edge connectors enabled independent contact to each of the 9 wells via gold traces routed through the chip, as shown in Fig. 1 . Lastly, a thin layer of Parylene C (a stable, reference dielectric material) was deposited (chemical vapor deposition) over the entire wafer, exposing only the connector tabs at the edge of the chips. Following fabrication, the individual chips may be diced from the wafers and stored for future testing. In this preliminary evaluation, Aelite All-Purpose dental composite (Bisco, Inc., Schaumburg, IL) was packed into 5 of the 9 test-wells (red arrow in Fig. 1 ) and light-cured for 40 s at 500 mW/cm 2 (per manufacturer’s instructions) (For interpretation of the references to color in this figure, the reader is referred to the web version of the article.).
